ABSTRACT

As the role of the field programmable gate arrays (FPGA) becomes more significant in larger and more complex system designs, it demands higher logic capacity and more on-chip resources and functionalities. Until 40 nm node, FPGAs have depended predominantly on Moore’s law scaling to respond to this need, delivering nearly twice the logic capacity with each new process generation. However, keeping pace with today’s high-end market demands requires more than what Moore’s law can provide.