ABSTRACT

Interest in packaging-based three-dimensional integration (3DI) technology using wafer-level processing has been increasing again. This is driven by the physical and economic limits of conventional scaling, which is no longer a main stream for the increasing demands for device performance, system form factor, and total manufacturing cost. This chapter discusses a back-end-of-line (BEOL)-compatible wafer-level 3DI approach including state-of-the-art interconnecting technologies such as bumpless vertical interconnects and ultrathinning of 300 mm wafers down to micrometer thickness.