ABSTRACT
This chapter is concerned with the manufacturing issues of complementary metal oxide semiconductor (CMOS). The Design-for-manufacturability (DfM) process is ongoing and starts resembling the classical, industrial concept originally developed for the automotive industry, as the CMOS technology reaches new levels of maturity. For isolated, straight channel metal oxide semiconductor field-effect transistors (MOSFETs), defined without lithography limitations, critical issues include all aspects of leakage, for example, isolation leakage, gate leakage, and gate-induced drain leakage. Improvement of the MOSFET ON/OFF current ratio, a performance boost is accomplished by the use of strained silicon. For device primitives such as individual MOSFETs or inverters, one can propose two approaches to reduce the within-die variability: increase minimum device geometries to improve printability and change layout aspect ratio to reduce proximity effects. For analog/Radiofrequency (RF) applications, device sensitivity to the parasitic resistance, capacitance is becoming a higher priority for layout techniques as compared to footprint reduction or pattern fidelity.
