ABSTRACT
The design of the clock and data recovery (CDR) circuit is the most challenging task in implementation of any wireline receiver. In this chapter, the authors provide an overview of common CDR architectures and describe the implementation of their key building blocks. They focus on the design of high-performance LC oscillators for CDR circuits. In a full-rate CDR circuit, the frequency of the recovered clock equals the incoming data rate, allowing a clock rising (or falling) edge to appear in the middle of every bit. Single-edge retiming avoids degradation of the quality of detection arising from the duty cycle mismatch of the clock signal. As the operation speed of CDR circuits increases, binary phase detectors that rely on samples of the data to provide the phase error information in the form of early or late signals, and achieve higher immunity to nonidealities of analog process become more popular.
