ABSTRACT
Complementary metal oxide semiconductor (CMOS) device scaling has increased the impact of process variability to the point where it is now regarded as a major roadblock to further scaling. The control of process fluctuations has not kept pace with rapidly shrinking device dimensions. Furthermore, the drive to improve performance has enticed device and circuit designers to operate at conditions that are more sensitive to variability. Characterizing variability in a more detailed way would allow designers to use the right amount of margins to obtain an optimal design that maximizes performance, power, and yield. In this chapter, various test structures are used to measure variability and analyze its systematic, random, within-die (WID), and die-to-die (D2D) components. The impact of different layout topologies on variation is investigated; the spatial correlation of ring oscillator frequencies and leakage current is characterized.
