Introduction

Reducing the time between initial specification and final implementation does not mean that any implementation is acceptable; final system quality is still expected. This supposes that a portion of the design time is spent executing simulations, or more generally in a verification process. The simulation of MPSoC based system is a challenge that only increases as we move forward in the design process. Typically, Register Transfer Level (RTL) simulation is not possible for the entire system. In addition, it requires emulation or prototyping in conjunction with a significant size of test vectors. An alternative way to ensure the quality of these types of systems is verification. Since formal verification techniques require a significant amount of specialized knowledge on the part of designers and testers, assertion-based verification techniques seem promising techniques for widespread use.