ABSTRACT
Networks-on-Chip (NoC) was proposed at the beginning of this century to handle the communication problem between large number of computational resources in modern applications [29]. NoCs first employed predefined 2D or 3D generalpurpose standard architectures, used in computer networks and multi processor systems, to realize NoC-based designs [237, 239]. However, as modern application requirements differ significantly, the use of standard architectures might not guarantee a specific level of performance. Therefore, Application-specific Networks-on-chip (ASNoC) was presented to customize NoC architectures according to application requirements and design constraints [27, 234, 284]. Moreover, in recent years, Autonomous Networks-on-Chip (ANoC) started to become a hot research area [294]. In the literature, ANoC is used to represent two types of on-chip networks. The first is the fault-tolerant network, which is capable of operating properly even in the event of components failure [304]. The second is the adaptable self-optimized network that could adjust itself dynamically to optimize certain performance and cost metrics [329]. In this chapter, we target these self-optimized networks by presenting a new methodology to optimize the underlying on-chip network architecture during runtime.
