ABSTRACT

With the stringent requirements on power and silicon area, building a processor with many cores has been widely accepted in the industry as the primary

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approach to continue delivering ever-increasing performance. Processors with tens to hundreds of cores, with aggregate performance exceeding one trillion operations per second are expected soon. Such tera-scale many-core processors will be highly integrated system-on-chip designs containing a variety of on-die storage elements, memory controllers, and input/output (I/O) functional blocks. As a result, the on-chip interconnect becomes a crucial factor in designing such highly integrated heterogeneous systems. Demanding workloads create hot-spots, jitters, and congestion during communication among various blocks. An adaptive interconnect capable of responding gracefully to such transients can address such issues. Other challenges, such as manufacturing defects, on-chip variations, and dynamic power management can also be better served through flexible and adaptive interconnect solutions.