ABSTRACT
Scalable on-chip networks define a new environment for network interfaces (NI) and communication of the interconnected devices. On-chip communicating nodes are usually involved in a computation framework, whose efficiency critically depends on the organization of resources as well as on the performance of the communication architecture. The principle of device networking was inspired by off-chip network architectures, such as those in the Local Area Network (LAN)/ Wide Area Network (WAN) or personal computer (PC) cluster domains, which however evolved in a different direction in
Era
light of their distinctive features, with complex protocols, robustness in the face of varying traffic patterns and latency not being a primary concern.
