ABSTRACT
This chapter tries to summarize our experience in the development of the analog front-end part of 2.4 GHz ZigBee transceivers with the main objective of optimizing power consumption during normal operation in both reception (described in Section 7.3) and transmission modes (at Section 7.4). Other interesting design aspects, such as optimizing the transceiver protocol, the design of the digital subsystems, or managing the sleep modes, have not been included due to space limitation. To gather together the presented design ideas, the chapter concludes in Section 7.5 with an example of a complementary metal-oxide semiconductor (CMOS) integrated transceiver analog front-end. The competitive experimental performances for this integration endorse the employed design flow, procedures, and analysis.
