ABSTRACT
The seemingly ever-increasing data rates and complexity of modern analog and RF integrated circuits (ICs) intensify the test effort that must be spent
CONTENTS
14.1 Introduction ................................................................................................349 14.2 Machine Learning-Based BIST Architecture .........................................350 14.3 Cost-Efficient Implementation of Neural Classifier .............................. 353 14.4 Analog Neural Network with Digital Weight Storage (ANNDW) ..... 355
14.4.1 Supported Neural Network Model ............................................. 355 14.4.2 System Architecture ...................................................................... 356 14.4.3 Synapse and Neuron Circuits ...................................................... 357 14.4.4 Hardware-Friendly Training Algorithm .................................... 359
14.5 Floating Gate-Based Analog Neural Platform .......................................360 14.5.1 Ontogenic Neural Network Model ............................................. 361 14.5.2 Chip Architecture .......................................................................... 361 14.5.3 Weight Storage ................................................................................ 362 14.5.4 Synapse and Neuron Circuits ......................................................364 14.5.5 ONN Training Algorithm .............................................................364
14.6 Case Study I: Parametric Faults (LNA Circuit) ......................................365 14.6.1 Problem Definition and DUT .......................................................365 14.6.2 Data Source .....................................................................................365 14.6.3 Dataset Enhancement ....................................................................368 14.6.4 Experimental Results .................................................................... 369
14.7 Case Study II: Defect Filter (RF Front-End) ............................................ 372 14.7.1 Problem Definition and DUT ....................................................... 372 14.7.2 Data Source ..................................................................................... 373 14.7.3 Experimental Results .................................................................... 373
14.8 Conclusions ................................................................................................. 375 References ............................................................................................................. 376
to guarantee the correct functioning of each manufactured part. Pushing device geometries to their physical limits has made them more susceptible to manufacturing process variations and defects. To ensure the compliance of each manufactured part to its specifications, hundreds of sequential tests are carried out in practice. This procedure demands sophisticated test equipment and creates a major bottleneck in the manufacturing throughput, thereby escalating significantly the overall manufacturing cost. As RF devices become a ubiquitous part of our everyday lives, there is a great incentive to reduce the implicated test costs, while maintaining the highest possible quality and reliability of the parts that pass the test.
