ABSTRACT
Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 12.3 Polar Code Emulation for Optimal Code Construction . . . . . . . . . 364
12.3.1 Introduction to Polar Code and Decoder Design . . . . . . . 365 12.3.2 Decoder Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
12.3.2.1 Decoder Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 367 12.3.2.2 FPGA Emulation Design . . . . . . . . . . . . . . . . . . . . . 368
12.3.3 Study of Polar Code Bit Selection Using Emulation . . . . 369 12.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
and
High-performance error-correcting codes (ECC), including turbo codes [1] and low-density parity check (LDPC) codes [2, 3], have been widely used for forward error correction (FEC) in modern communication systems. ECC has allowed these communication systems [4, 5, 6, 7, 8, 9, 10, 11] to dramatically reduce the signal-to-noise ratio (SNR) needed to achieve a given bit error rate (BER). These high-performance ECCs have also entered storage systems, including magnetic drives [12] and solid-state storage [13] to improve storage capacity and reliability.
