ABSTRACT
Video compression is the key enabling technology for multimedia communications. Without compression, digitized raw video data requires too much bandwidth and storage. Usually, the higher the compression ratio we want, the more complex the video coding algorithms that we have to apply. To realize complex video encoding or decoding, we need powerful VLSI circuits to do the computations in real-time.
The Advanced Video Coding (AVC; also known as ITU-T H.264 and MPEG-4 Part 10) standard was developed by the Joint Video Team (JVT), which consists of members of both the ITU-T Video Coding Experts Group (VCEG) and the ISO/IEC Motion Picture Experts Group (MPEG). AVC significantly outperforms previous video coding standards. Its high compression performance comes at a very high cost of computing and memory access. Furthermore, due to the complex, sequential, and highly data-dependent characteristics of the essential algorithms in AVC, both pipelining and parallel processing techniques are difficult to be directly employed. The hardware utilization and throughput are also decreased because of the inherent block/ macroblock/frame-level reconstruction loops.
In addition to the complexity issue, another big headache is the power consumption, especially for mobile applications. Allocating powerful hardware resources for realtime computing is the basic requirement. At the same time, we also have to consider the power optimization. For battery-powered appliances, the energy is limited, and no one can accept a product that needs to be charged frequently. An integrated circuit (IC) consuming too much power will also cause the heat dissipation and stability problem.
171In this chapter, three hardwired H.264/AVC encoder/decoder design cases are presented. The first design is an HDTV720p 30 frames/s AVC encoder. 1 , 2 From the discussions of this design, we can see how hardware resources are efficiently allocated to fulfill the computing requirement. The second case is the design of a low-power and power-aware AVC encoder. 3 Here, the target specification of video resolution is smaller, and the design puts more emphasis on power issues. Low-power techniques are discussed, and the power-awareness concept is realized in this power-scalable architecture. In the third reference design, the architecture of a hybrid task-pipelining AVC decoder 4 , 5 is described. The major design issue is to arrange decoding functions into proper pipelining schedules, and to reduce the external and internal memory bandwidth.
Before detailed discussions of the three design cases, a brief introduction and analysis of the H.264/AVC algorithm is given in section 8.1.
