Comparisons between two different current-voltage characteristics’ curves on FinFET devices

Drain Current (I_DS) versus Drain Bias (V_DS) and drain current versus Gate Bias (V_GS) both share the very same conventional formula of electrical characteristics’ curves. As drain and gate are applied with certain biases, the unknown physical quantities are left to be determined including the threshold voltage (V_th), mobility (μ), and lambda (λ). Nanometer-scale NFinFET devices fabricated on Silicon On Insulator (SOI) wafers to prevent the outrageously leakage current successfully win the designers’ satisfactions and are always taken into account in the future. Nevertheless, the algorithms are posed to fit the electrical characteristics’ curves in order to fully understand electrical performance. The two stage I_DS – V_DS are different from the three stage I_DS – V_GS in several aspects, especially the threshold voltage. The threshold voltage is unique in I_DS – V_GS while they are taken to be variables in I_DS – V_DS, depending on the gate bias. The authors use the fitting algorithms to partly explore some underlying physical features.