A wide-tuning frequency range DLL-based clock generator

A Wide-Tuning Frequency Range DLL-Based Clock Generator is presented, which is simulated by TSMC 0.18um CMOS process. The architecture of proposed Delay-Locked Loop consists of Start-up Circuit, Phase Detector, Lock Detector, Charge Pump, Wide-Range VCDL, and Edge Combiner. The proposed clock generator can generate clock signals ranging from 1GHz to 4GHz. The power consumption of the presented DLL is 15 mW at a 1.8 V of supply voltage.