ABSTRACT
A high bit modular multiplier based on novel design of Radix-4 Montgomery architecture in the layout design is presented in this paper. It is based on using two types of digit recoding which results in a competitive and increased in speed operation of the design, smallest transistor accounts and the power/speed ratio. We showed in previous publications that radix-4 multiplier operates at high speed and has relatively small area which makes it one of the best solutions in many arithmetic-dependent applications, such as public-key cryptography algorithms and signal processing applications. In this paper, we are investigating the power dissipation of the proposed architecture and we are presenting the hardware components using transmission gates which reduce the power dissipation at minimum value. The new design is implemented in 0.12-μm double-poly double-metal CMOS process, with 1.2 V power supply.
