ABSTRACT
Since the end of the 1990s, the microelectronics industry has been facing new challenges as far as CMOS devices scaling is concerned. Linear scaling will be possible in the future if new materials are introduced in CMOS device structures or if new device architectures are implemented. Innovations in the electronics history have been possible because of the strong association between devices and materials research. The demand for low voltage, low power and high performance are the great challenges for the engineering of sub 50 nm gate length CMOS devices because of the increasing interest and necessities of Nomadic Electronic Systems. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. In this chapter, alternative architectures that allow increase to devices’ drivability and reduce power consumption are reviewed such as multigate, multichannel architectures and nano wires. The issues in the field of gate stack, channel, substrate, as well as source and drain engineering are addressed. HiK gate dielectric and metal gate are among the most strategic options to implement for power consumption and low supply voltage management. By introducing new materials (Ge, Carbon based materials, III-V semiconductors, 6HiK, …), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating also new disruptive devices. For these devices, the low parasitics required to obtain high performance circuits, makes competition against logic CMOS extremely challenging.
