ABSTRACT
This chapter outlines some of the processing operations that are carried out in the visual cortex and considers how they might be carried out using a set of image-processing algorithms in a digital logic processing system. It examines some aspects of three-dimensional (3D) architectural considerations, in particular the question of how to reduce power dissipation by switching processing elements on or off as required, and how the processing elements in the layers in a 3D stack might be laid out. The chapter deals with a short description of the experimental setup that was used by the other CORTEX partners to make electrical measurements on molecular wires. It considers some structural and architectural aspects of a 3D computational system as envisaged in the CORTEX project. The chapter describes a possible means of reducing power consumption in 3D systems by using local activity control in Single Instruction, Multiple Data arrays—some quantitative results are described and discussed.
