ABSTRACT
Silicon-photonic links are an attractive alternative to traditional electrical interconnects in large manycore systems owing to the increased bandwidth-density, lower communication latencies, and negligible data-dependent power. Recent developments in CMOS process technology have resulted in mature 3D and 2.5D integration of photonic devices in silicon. However, a primary concern limiting the wide-spread adoption of silicon-photonic links in manycore system is the increased photonic power overhead. The power cost of laser sources and circuitry for electrical-optical-electrical (EOE) conversion increases with on-chip bandwidth. Additionally, the optical devices used in silicon-photonic links are highly sensitive to on-chip thermal variations and manufacturing process variations. Device-level techniques to thermally tune the optical devices and offset these variations require additional heating power. Therefore, managing the high-power cost of silicon-photonic links to support the increasing bandwidth-density demands of applications becomes a critical factor towards achieving energy-efficient computing.
In this chapter, we detail the thermal and process variation sensitivities of optical devices, and the device-level techniques to mitigate their impact. We then highlight a need for system-level management techniques that can address the bandwidth-power tradeoffs in silicon-photonic links. We introduce frameworks for cross-layer modeling and simulation of silicon-photonic links, focusing on how these frameworks account for the device-level characteristics and implement architectural and system-level optimizations to reduce the photonic power. We then present the runtime management techniques and system-level policies that achieve low-power operation of silicon-photonic links in several manycore system architectures.
