A novel low power BIST-TPG with reduced testing time

Power dissipation is the major problem in testing VLSI circuits. The application of random test input patterns causes high switching activity which increases dynamic power dissipation. The proposed Test Pattern Generator (TPG) generates test patterns with high correlation and reduces power dissipation in Circuit Under Test (CUT) with reduced test time. It identifies the consecutive test patterns that have more transitions and inserts test vectors in between them. Test vectors are formed using random bits which have low transitions. The results on ISCAS bench marks prove that the proposed method reduces the 72 % of dynamic power dissipation.