ABSTRACT
This paper presents a detailed state-space average model for the step down buck regulator including circuit parasitic. Presented work focuses on analyzing the effect of circuit non-idealities such as ESR of inductor and capacitor, switches on time resistant and series voltage drop on circuit performance. The averaging method is used to evaluate the system matrix of the time varying circuit model. Developed model is further used to analyze the effect of the circuit non-idealities on selection of duty cycle, stability margin for different loading condition and the open loop frequency response. Proposed model can be used to design robust controller that can satisfy the design requirement.
