ABSTRACT
Industry has come up with new strategies and techniques to cope up with the lower geometry challenges. These challenges are design scale, complexity, manufacturing requirements for lower node technology challenges like double patterning, FinFET statistical analysis and optimization capabilities to achieve Time, Area, and Power (TAP) on vigorous project timelines. The most important one is taping out ASIC on schedule is a milestone. Partitioning, geometry usage, routing/resource distribution, block execution has its own challenges and there is huge dependability on each block’s quality physical verification closure. As the transistor density increases, the designer is responsible for choosing the suitable or best trade off between Time, Area, and Power for the fast growing and improving technology at lower geometry. In this paper, we will see several Timing optimization techniques which can be used at different PNR stages, how the power, area like parameters are affected and how the best trade off should be selected which suits our design, at 28nm technology node of a complex networking ASIC chip.
