Design of FINFET based DRAM cell for low power applications

Low power has become an important factor in the design of Very Large Scale Integration (VLSI) circuits such as memory elements and digital systems. This paper reviews the power savings in a Dynamic Random Access Memory (DRAM) cell which is designed by using FinFET (Fin Field Effect Transistor). Applying this technique in the architecture of DRAM Cell, a reduction in overall power consumption has been approximately obtained. The proposed circuit has advantages in ultra-low power VLSI design. The circuit has been designed and implemented in H-spice at 32nm Technology.