ABSTRACT
This chapter discusses the Peripheral Component Interconnect Express (PCIe) bus that connects CPU and I/O, including the packet movement procedure between CPU and network interface card (NIC), along with a quantitative analysis of the PCIe bandwidth usage. It also explores the memory buffer and its performance optimization practices. It is important to understand the basic steps and then proceed to the optimal combinations. Memory buffers can be used for packet or control purposes, and the request is sent to Data Plane Development Kit (DPDK) mempool. All packets use mbufs, which are managed through the DPDK mempool interface. The mempool design is based on a ring concept, which manages the used/free mbuf objects for packet RX/TX. In this chapter, the PCIe interface, direct memory access, descriptor, and packet movement techniques and their optimizations are discussed. The packet descriptors and their related memory buffers in the context of NIC RX/TX are also discussed.
