ABSTRACT

The phase locked loop (PLL) is a control system that compares the phase of the output signal with that of the input signal and proportionally varies its output based on the phase difference between them. PLL most prolifically finds its applications in frequency generation, clock and data recovery, carrier frequency generation in modulation and demodulation, frequency synthesizers, jitter and skew reduction, and many more. Mixed-signal and digital circuits employ PLL for clock generation to get the synchronous transactions with the clock. So it is mandatory to properly design the PLL to obtain minimum jitter on the clock edges. The PLL designed in this work was based on the famous charge-pump (CP) architecture and was implemented using the semiconductor laboratory (SCL) 180 nm technology in Cadence Virtuoso. This work uses NOR-based PFD using TSPC latches, Transmission gate CP, Current Starved VCO, and TSPC-based divider circuit. The proposed model of PLL has phase noise of the PLL as −113 dBc/Hz, the power consumption of the total PLL as 3.2 mW at 1.8 V power supply with deterministic jitter of about 5.62 ps and the settling time of the control voltage as 850 ns.