ASAP7: A finFET-Based Framework for Academic VLSI Design at the 7 nm Node

This chapter focuses on the development of a realistic process design kit (PDK) for academic use that overcomes certain limitations. The PDK, developed for the N7 node before 7 nm processes were available even in industry, is thus predictive. The predictions have been based on publications of the continually improving lithography, as well as our estimates of what would be available at N7. For the most part, these assumptions have been accurate, except for the expectation that extreme ultraviolet (EUV) lithography would be widely available, which has turned out to be optimistic. The background and impact on design technology co-optimization (DTCO) for standard cells and static random access memory (SRAM) comprises this chapter.