ABSTRACT
High-speed frequency synthesis is one of the most challenging areas in radio frequency integrated circuit (RFIC) design. A high-performance frequency synthesizer is a key component in many wired and wireless communication systems. For modern multistandard applications, it is often difficult to cover multiple frequency bands using classical integer-N frequency synthesizers whose step size is limited by the reference frequency. To achieve fine step size to cover the multiband channel frequencies, one has to lower the reference frequency in an integer-N synthesizer design, which results in high division ratio of the phase-locked loop (PLL) and thus high in-band phase noise. The chapter presents a theoretical analysis of phase noise in modern frequency synthesizers. It also presents a review of basic phase noise concepts, followed by a model that will allow the designer to take noise data from individual circuit simulations and predict the overall phase noise performance of an entire PLL frequency synthesizer.
