ABSTRACT
This chapter explores the various components of leakage currents at the transistor level, and describes the effect of leakage currents at the circuit level. The “stack effect” refers to the leakage reduction effect in a transistor stack when more than one transistor is turned off. When stacked devices are turned off, the time required for the leakage currents to settle to the previously computed steady-state leakage levels can be large and can vary widely, ranging from microseconds to milliseconds. Many techniques have been reported in the literature to reduce leakage power during standby condition. Punchthrough occurs when the drain and source depletion regions approach each other and electrically “touch” deep in the channel. The chapter concludes with a few techniques that can be used to help control subthreshold leakage currents in both sleep and active circuit modes. Many techniques have been reported in the literature to reduce leakage power during standby condition.
