ABSTRACT

This chapter provides a general framework for the design of low-power systems on chips (SoCs), starting from the system level to the architecture level, assuming that the SoC is mainly based on the reuse of low-power processors, memories, and standard cell libraries. Low-power software techniques have to be applied to each piece of software, including pruning, inlining, loop unrolling, and so on. Power estimation at high level is a very useful tool to verify the estimated total power consumption. Quite a large number of low-power techniques have been proposed for hardware but relatively fewer for software. Hardware designers are at least conscious that power reduction of SoCs is required for most applications. The low-power techniques used were the branch-based logic style that reduces parasitic capacitances and a clever transistor sizing. Instead, to enlarge transistors to have more speed, parasitic capacitances were reduced by reducing the sizes of the transistors on the cell critical paths.