ABSTRACT
This chapter begins with a discussion of some of the existing test methodologies and the key issues/requirements associated with the testing of System-on-Chip (SoC). Traditional scan implementation depended on the “over-the-wall” approach, where designers complete the synthesis and hand off the gate netlist to the test engineer for test insertion and automatic test pattern generation. Test challenges arise both due to the technology and the design methodology. Two major capabilities are needed to address the major test challenges: making the core test-ready and integration of test-ready cores and user logic at the chip level. A ready-to-test core provides complete transparency to the SoC designer. Core test language is a language that describes all the necessary information about test aspects of the core such that the test patterns of the core can be reused and the logic outside the core can be tested in the presence of the core.
