ABSTRACT
Emitter-coupled logic (ECL) circuits have often been employed in very high-speed very large scale integration circuits. However, a passive pull-down scheme in an output stage results in high power dissipation as well as slow pull-down transition. An ECL inverter circuit is depicted together with the simulated output voltage and pull-down current waveforms. Demand for low-power dissipation has motivated scaling of a supply voltage of digital circuits in many electronic systems. Reducing the supply voltage of ECL circuits is becoming important not only to reduce the power dissipation but also to have ECL and Complementary metal oxide semiconductor circuits work and interface together, under a single power supply on a board or on a chip. Gate stacking in ECL is effective in reducing the power dissipation because complex logic can be implemented in a single gate with fewer current sources.
