ABSTRACT
An enhanced device structure employing gate engineering on the planar gate power VDMOS has been implemented here. The device GE VDMOS employs N+ and P+ polysilicon gate material in conjunction with different oxide thickness at the gate. This modification provides better performance parameters of GE VDMOS when compared with conventional VDMOS. 25% reduction in specific resistance of GE VDMOS is achieved in linear region of operation. Further, the proposed device exhibits 58% increment in CGS and 10% reduction in CGD implying enhanced switching speed. Through simulation results, it has been revealed that GE VDMOS offer 21% reduction in switching delay at same value of breakdown voltage.
