ABSTRACT
Rate-limiting processes in drain lag phenomena in HJFETs (Heterojunction Field Effect Transistors) on hole-trap substrates are investigated by using numerical simulation with SRH statistics for deep-level traps. The slow drain-current responses for HJFETs on floating substrates are determined by electron capture and emission even for hole-trap substrates, since total hole concentration is kept constant. In addition, time constants are much smaller than those estimated from SRH statistics since charge variation is enhanced by internal hole movement. On the other hand, drain-lag time constants for HJFETs with substrate electrodes are determined by the hole current travelling through the substrate from the electrode to the trap. These results indicate that special care should be taken in determining the trap parameters causing drain lag in FETs from time constant measurements.
