ABSTRACT
We describe a novel type of GaAs FET using LT GaAs as a lossy dielectric. In this device, between gate and drain, an LT GaAs surface layer is used as a low conductive bypass with linear IV characteristics providing a controlled leakage path. This leads to a field redistribution in the high field space charge and drift region which lowers the maximum field and improves the breakdown characteristics. Experimentally a high power density is observed at 1 MHz of up to 2.7 W/mm. At higher frequencies, the output power decreases down to 0.6 W/mm. We propose to explain this reduction by a new mechanism based on the charge density distribution in the LT GaAs which leads to the formation of a parasitic second gate. This parasitic gate compresses the maximum available open channel current and RF power density. We propose an experimental optimisation of the structure, where the current compression has not been observed while high current levels and breakdown voltages are still maintained. From large signal measurements at 0.85 GHz a maximum output power density of 1.75 W/mm is extracted. We discuss this experimental window and compare to theoretical expectations.
