ABSTRACT
1 INTRODUCTION
Very large scale integration (VLSI) technologists are fast developing wafer-scale integration [1], Rather than partitioning a silicon wafer into chips as is usually done, the idea behind wafer-scale integration is to assemble an entire system (or network of chips) on a single wafer, thus avoiding the costs and performance loss associated with individual packaging of chips. A major problem with assembling a large system of microprocessors on a single wafer, however, is that some of the processors, or cells, on the wafer are likely to be defective, or dead. In this chapter we present algorithms to construct systolic arrays from the live cells of a silicon wafer.
