ABSTRACT
The prime focus of this chapter is to evaluate the performance of a novel channel engineered junctionless double-gate (JLDG) MOSFET in the field of radiation sensing and low-power circuit application based on CMOS technology. However, the short-channel behaviour of the proposed MOSFET structure is shown to analyse the device characteristics, which is a pivotal parameter in the case of low-power applications. Besides, the proposed JLDG MOSFET has been considered as a radiation sensitive FET by incorporating interface trap charges (uniform and non-uniform) at the interface of SiO2 and silicon. In addition to this, the chapter also includes the design and analysis of DC characteristic parameters of a CMOS inverter in the form of power dissipation, propagation delay, noise margin, power–delay product (PDP) or energy etc. based on the novel channel engineered JLDG MOSFET. Complete simulation is performed with the help of a SILVACO ATLAS simulator. The proposed MOSFET shows impressive results in terms of short-channel behaviour, high sensitivity (radiation sensing), ultra-low power dissipation, faster operating speed, high noise margin etc. in the case of inverter performance analysis.
