ABSTRACT
Semiconductor devices are taking portable device manufacturing to a different level. According to the consumer requirements, these devices are scaled down so that they can be more user-friendly and handy to use. As MOSFET is the building block for all these devices, its downscaling is the most important task to be performed. Transistor count no longer increases on a trajectory following Moore’s law; in today’s world, it is no longer just about Moore. In order to scale down the devices into the next technology node, device dimension scaling is not the ultimate solution. Different material engineering techniques should be followed to take the miniaturization to a different level. Dramatic changes in the semiconductor industry in the past few decades to improve device performance have been accompanied by the shrinking of the size of logic and memory devices. This scaling requires drastic reduction in the size of dielectric to achieve higher capacitive densities. Introducing high-k dielectric in place of normal dielectric provides the opportunity to scale down the device to next level. The dielectric with low-k cannot scale down below 1 nm (fundamental limit), as it will not behave as dielectric anymore, so high-k is the ultimate solution for these types of device dimensions. However, the need to lay the high-k material over silicon body creates some fabrication issues, which can be resolved by introducing a thin interfacial layer in between.
