ABSTRACT
Incessant downscaling of advance CMOS devices have led device engineers to consider their placement of SiO2 and SiON layers with high-k gate dielectrics like HFO2, TiO2, and HfSiO(N). Intensive research has been carried out so far to develop these oxides into high-quality electronic materials. As per the specifications required by International Technology Roadmap for semiconductors, these gate oxides have felicitated in drastically reducing the leakage current. However, major problem remains unsolved before the possible use of high-k gate dielectric-based devices. The purpose of this chapter is to provide an in-depth analysis of the challenges in conventional CMOS technology and various issues pertaining to high-k gate dielectrics-based devices. It covers several technical and scientific challenges like choice of oxides, oxide deposition, their metallurgical and structural behavior, interface structure, charge trapping, flat band voltage, carrier mobility degradation, electronic defects, threshold voltage control, and gate dielectric wear and breakdown to achieve the oxide thickness as thin as possible. The combination of metal gates with high-k gate dielectrics seems to be a promising viable solution for further downscaling of CMOS-based devices. Besides this, high-k gate dielectrics-based devices like Tunnel FET are also discussed at length.
