ABSTRACT
Since the original proposal of Tiwari et al., 1 nanocrystal (NC) flash memories became widely investigated in the literature due to many 934advantages in comparison to the well established floating gate memories. Those advantages are as follows: faster operation, longer retention times, lower power consumption, and enhanced reliability and scalability. From the experimental point of view, advances in this field are tremendous. Many different approaches to fabricate NC memories were suggested, whereas the most important seems to be (i) the replacement of SiO2 oxide by high-x dielectrics, 2–4 (ii) the use of different device architectures like silicon-on-insulator substrates 5 and fin field-effect transistors, 6 and (iii) the replacement of Si by Ge as the NC material. 7 From the theoretical point of view, many groups have addressed charging/discharging processes using different approaches like self-consistent Schrödinger–Poisson scheme including single electron charging effects, 8–14 and Wentzel-Kramers-Brillouin-based formulations of the tunneling current. 7 , 15 , 16 However, little effort has been done to understand the role of traps in the device operation. One of the few attempts was done by Campera et al., 17 which modeled the experimental data of De Salvo et al., 18 and concluded that electrons are stored in defects in the NC/oxide interface. However, there are other works in the literature reporting that the NC states can also trap electrons. 19 , 20 In this letter, we model the charging/discharging dynamics in Ge NC flash memories with a realistic quantum mechanical model based on the density functional theory (DFT). From the differences between experimental and theoretical data, we show that electrons are confined in both NC states and surface defects and present a clear view of the action mechanism of the surface defects in the device operation.
