ABSTRACT
74This chapter describes the Cache Memory Design for Single Bit Architecture for IoT approaches to industrial informatics. Single Bit Architecture composed of six transistors static random access memory cell, a circuit of write driver, voltage differential sense amplifier, current differential sense amplifier, charge transfer differential sense amplifier, voltage latch type sense amplifier, and current latch-type sense amplifiers have been implemented and compared on different values of resistance. Results showed that the cache memory design for singe-bit architecture with voltage differential sense amplifier consumes 11.34 µW of power. Apart from it, power reduction techniques such as power reduction sleep transistor technique, power reduction forced stack technique, power reduction sleepy stack technique, and power reduction dual sleep technique is applied over different blocks of cache memory design for single bit architecture. The conclusion arises that Cache Memory Design for six transistors static random access memory cell with power reduction forced stack technique voltage differential sense amplifier with power reduction dual sleep technique in architecture consume 8.078 µW of power with the lowest 30.48 × 62.613 mm2 of area.
