ABSTRACT
Over the last five decades, researchers have been downsizing complementary metal–oxide–semiconductor (CMOS) electronics to accomplish effective execution regarding speed, power blow-out, size, and unwavering quality. Our motive is to make the general electronics that use gadgets such as PCs progressively smaller size, better speed, and mini power utilization. The scaling of CMOS is done to accomplish pace and decrease memory size. Static Random Access Memory (SRAM) is used to store information in convenient gadgets. Presently, 6T (6 transistor) SRAM is more favored than 8T and 9T in light of the fact that 6T SRAM cell gives a very low delay when contrasted with 8T and 9T SRAM and, furthermore, the power dissipation is half of what is dissipated in 8T and 9T SRAM. This paper acquiesces the design and realization of 6T SRAM bit cell in 180 nm, 90 nm, and 45 nm CMOS technology on cadence virtuoso EDA tool. The performance characteristics of 6Transistor Static RAM has been evaluated with reference to power and delay.
