ABSTRACT
D flip-flops (DFFs) are of two basic types: static and dynamic. This paper focuses on dynamic DFF. The dynamic nature comes with clock and reset configuration in true single-phase clocked (TSPC). The clock and rest signal consumes a lot of power when it comes to its work and switching activity. This makes it an important research area where it is necessary to improve the power consumption of the TSPC-based DFF. Below 22 nm, due to effects like DIBL or GIBL, power consumption rises, which also needs to improve. In this paper, a new TSPC-based DFF is proposed for a low-power application with Multi-Threshold CMOS (MTCMOS) Logic sleep signal insertion to reduce the power consumption for low-power applications. This works uses low-power-based MOS like GNRFET to reduce the short channel effects in MOS. This focuses on low power by the use of GNRFETs in 22 nm technology.
