ABSTRACT
In the field of technological advancement, researchers are continuously trying to improve the technology to make it better than before. In this proposed work, we use an algorithm to design an ALU-based FIR (Finite Impulse Response) filter. Basically, adder and multiplier are the main internal components of the ALU block in this 16- tap FIR filter. Multipliers and Adders (Floating Point) are used in the ALU (Arithmetic Logic Unit) block. These are the main parts of proposed architecture of FIR filter. This FIR filter architecture can be reduced its chip area and power consumption. Initially, the value of 16 input samples and 16 coefficients are obtained directly from a 16-tap filter using MATLAB software and then converted them into IEEE 754 standard forms. As a result, the proposed technique achieves 47 mW power and 16.4% reduction in area from conventional FIR filter design. Furthermore, HDL synthesis result shows power and area of the filter. The final simulation and the synthesis of proposed architecture is done by Xilinx ISE suite 14.7 software.
