ABSTRACT
Silicon fin-shaped field-effect transistors (FinFETs) have been first introduced in 22 nm node by enhancing gate-to-channel controllability over planar MOSFETs. As the self-aligned double patterning scheme is highly sophisticated, the fin shape changes from tapered to rectangular in 14 nm node, and a much taller and thinner fin has been formed in 10 nm node. Also, thorough design-technology co-optimization (DTCO), both front-end-of-line (FEOL) and middle-of-line (MOL) schemes are improved concurrently to improve the devices in the perspectives of performance (speed), power, and area (PPA). For example, removal of the dummy gate between active devices (single diffusion break) increases the device density greatly. Self-aligned gate and drain contacts reduce the M0 size by using materials with different etching selectivity. DTCO, with help from extreme ultraviolet lithography (EUV) for ultra-fine patterning, makes conventional device scaling feasible down to 5 nm node. In this chapter, we address conventional bulk FinFETs from 10 nm, 7 nm to sub-5-nm nodes. DC/AC performances among three different nodes were compared in terms of channel stresses, physical parameters, and capacitances. Finally, a novel process scheme possibly compatible under conventional process is introduced to scale down bulk FinFETs further in the 2 nm node.
