ABSTRACT
Communication systems have grown large and complex in terms of technology and implementation. With an unpredicted increase in the need of communications, several systems such as integrated ranging communication systems (ICRSs), which house a modern quadrature phase shift keying (QPSK) system for communication, need optimization in terms of power consumption. As tunnel FETs (TFETs) are a promising substitute for complementary metal oxide semiconductors (CMOSs) beyond the 45 nm level, to increase the performance of the QPSK system, an independent gate heterojunction TFET (IG HJ-DGTFET) has been designed to minimize leakage power and produce higher transconductance (g m), which ultimately improves the gain-bandwidth product (GBP). As the technology node scales down, the density of transistors becomes high producing higher power dissipation, which can reduce the longevity of the system. For designing the circuits of the X-OR gate and multiplexer, which are needed in the QPSK system, IG HJ-DGTFET with a 30 nm technology node is used. To reduce the complexity in the circuit level, a NAND gate has been designed, which is the leaf cell of D flip-flop. To account for the low static power consumption and complexity in X-OR gate, pass transistor logic (PTL) is used. The designed two input NAND and X-OR gates consume very less power and provide less propagation delay. Furthermore, the variations of the rise and fall time in the inverter transient characteristics due to temperature variations are observed to be insignificant in the QPSK system. This reveals that the circuits designed with IG HJ-DGTFET have an advantage of less temperature dependence.
