ABSTRACT
This chapter addresses overall memory design techniques for future technology nodes. In the introduction, the memory structures for next-generation memory are covered, and their advantages over conventional memory structures are addressed. Then, three main factors for memory design—low power, large memory margin, and long retention (3Ls)—are explained, and two optimization techniques are presented as a method to achieve these three factors. For the first optimization method, a stack-engineering technique is proposed for 3Ls. Memory designing using low-power FET (tunnel FET) is suggested as the second optimization method for low-power operation and erase speed improvement. Finally, this chapter is concluded by addressing four expected issues that could arise when designing next-generation memory devices using these optimization techniques.
