ABSTRACT
Over the past six decades, the semiconductor research community has been primarily governed by the ongoing trend of device dimension miniaturization to explore various non-conventional devices with reduced power consumption and enhanced speed to achieve high package density state-of-the-art integrated circuits having superior performance metrics. Tunnel FETs, with their fundamental characteristics of achieving steep sub-threshold slope, have become one of the most promising alternatives for ultra-low power applications. In this chapter, we shall present an in-depth insight on the device physics and analytical modeling of work function engineered gate novel Tunnel FET structures where modulation of gate metal work-function improves device performance in terms of higher ON current to OFF current ratio (ION/IOFF) and steeper sub-threshold slope.
