ABSTRACT
Low-area energy-efficient security primitives are key building blocks for enabling end-to-end content protection, user authentication, and consumer confidentiality in the IoT world that is estimated to surpass 50billion smart and connected devices by 2020. This chapter describes design approaches that blend energy-efficient circuit techniques with optimal accelerator micro-architecture datapath, and hardware friendly arithmetic to achieve ultra-low energy consumption in security platforms for seamless adoption in area/battery constrained and self-powered systems. Advanced Encryption System, True Random Number Generator, Physically Unclonable Functions are some of the key primitives that enable hardware acceleration of a significant number of security applications targeted for advanced content protection, signature generation and verification protocols. Poor energy-efficiency and diminishing performance resulting from implementing these security protocols in general purpose processors necessitate hardware acceleration to meet real-time throughput demands under a limited power budget.
