ABSTRACT
Modern RF frequency synthesizer designs are driven by ever increasing system requirements such as low power (e.g., for mobile devices, sensors, wearables, and internet of things, etc.), low phase noise (e.g., for wideband modulations such as 64~256 QAM, etc.) and multi-phase clock generations (e.g., for beam forming, phase array, N-path filtering, passive-mixing and interleaved data converters). Traditional LC based PLLs occupy large area and present challenges for technology scaling. On the other hand, area efficient ring oscillators often suffer from poor jitter and phase noise performances. Recent techniques including injection locking and sub-sampling have achieved impressive in-band noise performance. As a result, the integrated phase noise of inductor-less PLLs can be greatly improved with a widened loop bandwidth. Improving spectral purity is normally obtained at the price of higher power consumption.
