ABSTRACT
Sub-sampling-phase-locked loops (SSPLLs) enable low-noise frequency synthesis because of its high-loop-gain characteristics, leading to low-power analog building blocks. This chapter introduces the principle of sub-sampling PLLs and explains the concept of fractional-N synthesis. It covers the detail implementation and analysis for GHz frequency synthesis. Subsampling techniques cannot be employed in some applications which requires low noise fractional-N synthesizers for better frequency resolution. The major difference between analog and digital PLLs is in Phase comparison and loop filter. The filter in analog PLL needs passive components, including resistor and capacitor. If PLLs need to operate in wide range, it might be difficult to program the loop filter. On the other hand, digital PLLs employ a time-to-digital converter to digitize the phase difference. For loop filter design, digital PLLs only need digital cells to fulfil the function. Finally, power consumption might be high if digital PLLs are not implemented in nanometer technologies.
